marcorealacci/master-degree-notes
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

vault backup: 2025-04-05 00:07:51

Browse source
This commit is contained in:
Marco Realacci 2025-04-05 00:07:51 +02:00
parent 47b74f3eec
commit 1c82ee3d9d
11 changed files with 30 additions and 30 deletions
Download patch file Download diff file Expand all files Collapse all files

2
Concurrent Systems/notes/5 - Software Transactional Memory.md
View file

@ -105,7 +105,7 @@ The **casual past** of a transaction T is the set of all T' and T'' such that
VWC allows more transactions to commit -> it is a more liberal property than opacity.
![](Concurrent%20Systems/notes/images/Pasted%20image%2020250317105355.png)
![](images/Pasted%20image%2020250317105355.png)
#### A Vector clock based STM system
We have m shared MRMW registers; register X is represented by a pair XX, with: