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Concurrent Systems/notes/5 - Software Transactional Memory.md
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@ -105,7 +105,7 @@ The **casual past** of a transaction T is the set of all T' and T'' such that
VWC allows more transactions to commit -> it is a more liberal property than opacity.
![[/Concurrent Systems/notes/images/Pasted image 20250317105355.png]]
![](Concurrent%20Systems/notes/images/Pasted%20image%2020250317105355.png)
#### A Vector clock based STM system
We have m shared MRMW registers; register X is represented by a pair XX, with: