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Marco Realacci 2025-04-03 00:55:03 +02:00
parent 2b56eadbd1
commit 57a24ed0b0
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6
Concurrent Systems/test/Untitled.md
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@ -37,12 +37,12 @@ end_write() :=
``` ```
monitor RW_READERS := monitor RW_READERS :=
AR, WR, AW, WW init at 0 AR, WR, AW, WW, R_batch init at 0
condition CR, CW, CR_PR condition CR, CW
operation begin_read() := operation begin_read() :=
WR++ WR++
if AW != 0 then if (WW || AW != 0 then
CR.wait() CR.wait()
CR.signal() CR.signal()
AR++ AR++