marcorealacci/master-degree-notes
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

vault backup: 2025-04-04 23:35:23

Browse source
This commit is contained in:
Marco Realacci 2025-04-04 23:35:23 +02:00
parent 96872ffa06
commit 6a9cf80167
13 changed files with 28 additions and 28 deletions
Download patch file Download diff file Expand all files Collapse all files

2
Concurrent Systems/notes/5 - Software Transactional Memory.md
View file

@ -105,7 +105,7 @@ The **casual past** of a transaction T is the set of all T' and T'' such that
VWC allows more transactions to commit -> it is a more liberal property than opacity.
![[Pasted image 20250317105355.png]]
![[images/Pasted image 20250317105355.png]]
#### A Vector clock based STM system
We have m shared MRMW registers; register X is represented by a pair XX, with: