vault backup: 2025-03-03 09:42:47
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@ -108,7 +108,34 @@ We will consider different computational models according to the available level
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Atomic R/W registers are storage units that can be accessed through two operations (READ and WRITE) such that
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Atomic R/W registers are storage units that can be accessed through two operations (READ and WRITE) such that
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1. Each invocation of an operation
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1. Each invocation of an operation
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- locks instantaneous (it can be depicted as a single point on the timelinethere exist $t : OpInv \to R+$)
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- locks instantaneous (it can be depicted as a single point on the timeline: there exist $t : OpInv \to R+$)
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- may be located in any point between its starting and ending time
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- may be located in any point between its starting and ending time
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- does not happen together with any other operation
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- does not happen together with any other operation ($t$ is injective)
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2. Every READ returns the closest preceeding value written in the register, or the initial value (if no WRITE has occurred).
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2. Every READ returns the closest preceding value written in the register, or the initial value (if no WRITE has occurred).
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### Peterson algorithm (for two processes)
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Let's try to enforce MUTEX with just 2 processes.
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1st attempt:
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```
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lock(i) :=
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AFTER_YOU <- i
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wait AFTER_YOU != i
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return
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unlock(i) :=
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return
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```
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This protocol satisfies MUTEX, but suffers from deadlock (if one process never locks).
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2nd attempt:
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```
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Initialize FLAG[0] and FLAG[1] to down
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lock(i) :=
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AFTER_YOU <- i
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wait AFTER_YOU != i
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return
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unlock(i) :=
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return
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```
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