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7
Concurrent Systems/notes/5 - Software Transactional Memory.md
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@ -105,3 +105,10 @@ The **casual past** of a transaction T is the set of all T' and T'' such that
VWC allows more transactions to commit -> it is a more liberal property than opacity.
![[Pasted image 20250317105355.png]]
#### A Vector clock based STM system
We have m shared MRMW registers; register X is represented by a pair XX, with:
- XX.val the current value of X
- XX.depend[1...m] a vector clock s.t.
- XX.depend[X] is the sequence number associated with the current value of X
- XX.depend[Y] is the sequence number associated with the value of Y on which the current value of X depends from