diff --git a/Ingegneria del Software/0922_10/correct.txt b/Ingegneria del Software/0922_10/correct.txt new file mode 100644 index 0000000..cefc84a --- /dev/null +++ b/Ingegneria del Software/0922_10/correct.txt @@ -0,0 +1,69 @@ +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 0) and (pre(u) == 1) then x := 2; + +elseif (pre(x) == 0) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 1) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 1) and (pre(u) == 2) then x := 4; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 3) and (pre(u) == 1) then x := 1; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 4; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 0; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 1; + +elseif (pre(x) == 4) and (pre(u) == 2) then x := 1; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_10/quest.txt b/Ingegneria del Software/0922_10/quest.txt new file mode 100644 index 0000000..9dd6e3b --- /dev/null +++ b/Ingegneria del Software/0922_10/quest.txt @@ -0,0 +1,2 @@ +img=https://i.imgur.com/okpLYQL.png +Quale dei seguenti modelli Modelica rappresenta lo state diagram in figura ? \ No newline at end of file diff --git a/Ingegneria del Software/0922_10/wrong 1.txt b/Ingegneria del Software/0922_10/wrong 1.txt new file mode 100644 index 0000000..cc2b129 --- /dev/null +++ b/Ingegneria del Software/0922_10/wrong 1.txt @@ -0,0 +1,67 @@ +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 0) and (pre(u) == 1) then x := 4; + +elseif (pre(x) == 0) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 1) and (pre(u) == 0) then x := 3; + +elseif (pre(x) == 1) and (pre(u) == 1) then x := 0; + +elseif (pre(x) == 1) and (pre(u) == 2) then x := 0; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 3; + +elseif (pre(x) == 3) and (pre(u) == 1) then x := 4; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 4; + +elseif (pre(x) == 4) and (pre(u) == 2) then x := 0; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_10/wrong 2.txt b/Ingegneria del Software/0922_10/wrong 2.txt new file mode 100644 index 0000000..f0f54bf --- /dev/null +++ b/Ingegneria del Software/0922_10/wrong 2.txt @@ -0,0 +1,69 @@ +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 0) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 1) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 1) and (pre(u) == 1) then x := 0; + +elseif (pre(x) == 1) and (pre(u) == 2) then x := 3; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 3) and (pre(u) == 0) then x := 0; + +elseif (pre(x) == 3) and (pre(u) == 1) then x := 1; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 0; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 1; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_11/correct.txt b/Ingegneria del Software/0922_11/correct.txt new file mode 100644 index 0000000..2fd674f --- /dev/null +++ b/Ingegneria del Software/0922_11/correct.txt @@ -0,0 +1 @@ +60% \ No newline at end of file diff --git a/Ingegneria del Software/0922_11/quest.txt b/Ingegneria del Software/0922_11/quest.txt new file mode 100644 index 0000000..55e0e6a --- /dev/null +++ b/Ingegneria del Software/0922_11/quest.txt @@ -0,0 +1,19 @@ +img=https://i.imgur.com/im1GU0x.png +La transition coverage di un insieme di test cases (cioè sequenze di inputs) per uno state diagram è la percentuale di transizioni (archi nel grafo dello state diagram) percorsi almeno una volta. + +Si consideri lo state diagram in figura + + +ed il seguente insieme di test cases: + + + +Test case 1: act2 act1 act2 act2 + +Test case 2: act2 act2 act1 act2 act1 act2 act1 act2 act1 act2 act2 act1 act1 act2 act1 act2 act2 act2 + +Test case 3: act2 act2 act0 + + + +Quale delle seguenti è la migliore stima della transition coverage per i test cases di cui sopra? \ No newline at end of file diff --git a/Ingegneria del Software/0922_11/wrong 1.txt b/Ingegneria del Software/0922_11/wrong 1.txt new file mode 100644 index 0000000..95bc750 --- /dev/null +++ b/Ingegneria del Software/0922_11/wrong 1.txt @@ -0,0 +1 @@ +100% \ No newline at end of file diff --git a/Ingegneria del Software/0922_11/wrong 2.txt b/Ingegneria del Software/0922_11/wrong 2.txt new file mode 100644 index 0000000..a2507e5 --- /dev/null +++ b/Ingegneria del Software/0922_11/wrong 2.txt @@ -0,0 +1 @@ +80% \ No newline at end of file diff --git a/Ingegneria del Software/0922_12/correct.txt b/Ingegneria del Software/0922_12/correct.txt new file mode 100644 index 0000000..1e091a3 --- /dev/null +++ b/Ingegneria del Software/0922_12/correct.txt @@ -0,0 +1 @@ +90% \ No newline at end of file diff --git a/Ingegneria del Software/0922_12/quest.txt b/Ingegneria del Software/0922_12/quest.txt new file mode 100644 index 0000000..dd553a4 --- /dev/null +++ b/Ingegneria del Software/0922_12/quest.txt @@ -0,0 +1,17 @@ +img=https://i.imgur.com/rWKWcCt.png +La transition coverage di un insieme di test cases (cioè sequenze di inputs) per uno state diagram è la percentuale di transizioni (archi nel grafo dello state diagram) percorsi almeno una volta. + +Si consideri lo state diagram in figura + + +ed il seguente insieme di test cases: + +Test case 1: act2 act0 act2 act2 act0 act1 act1 act0 act0 act2 act0 act2 act2 act2 act1 act2 act2 act0 act0 act2 act1 act0 act0 act2 act2 act2 act0 act2 act2 act0 act2 act0 act1 act2 act1 act1 act1 act1 act0 act1 act0 act1 act2 act1 act2 act0 + +Test case 2: act0 + +Test case 3: act2 act0 act2 act2 act0 act2 act0 act2 act2 act2 act0 act0 act1 act2 act0 act2 act2 act0 act2 act2 act0 act2 act0 act2 act2 act2 act0 act1 act1 act1 act0 act0 act1 act1 act2 act0 act0 act2 act1 act0 act2 act2 act0 act2 act2 act0 act0 act2 act0 act1 act0 + + + +Quale delle seguenti è la migliore stima della transition coverage per i test cases di cui sopra? \ No newline at end of file diff --git a/Ingegneria del Software/0922_12/wrong 1.txt b/Ingegneria del Software/0922_12/wrong 1.txt new file mode 100644 index 0000000..95bc750 --- /dev/null +++ b/Ingegneria del Software/0922_12/wrong 1.txt @@ -0,0 +1 @@ +100% \ No newline at end of file diff --git a/Ingegneria del Software/0922_12/wrong 2.txt b/Ingegneria del Software/0922_12/wrong 2.txt new file mode 100644 index 0000000..23e721f --- /dev/null +++ b/Ingegneria del Software/0922_12/wrong 2.txt @@ -0,0 +1 @@ +50% \ No newline at end of file diff --git a/Ingegneria del Software/0922_13/correct.txt b/Ingegneria del Software/0922_13/correct.txt new file mode 100644 index 0000000..23e721f --- /dev/null +++ b/Ingegneria del Software/0922_13/correct.txt @@ -0,0 +1 @@ +50% \ No newline at end of file diff --git a/Ingegneria del Software/0922_13/quest.txt b/Ingegneria del Software/0922_13/quest.txt new file mode 100644 index 0000000..7e33553 --- /dev/null +++ b/Ingegneria del Software/0922_13/quest.txt @@ -0,0 +1,15 @@ +img=https://i.imgur.com/em6ovKG.png +La transition coverage di un insieme di test cases (cioè sequenze di inputs) per uno state diagram è la percentuale di transizioni (archi nel grafo dello state diagram) percorsi almeno una volta. + +Si consideri lo state diagram in figura + + +ed il seguente insieme di test cases: + +Test case 1: act2 act0 + +Test case 2: act2 act1 act2 act0 act0 act0 act1 act0 act0 act1 act0 + +Test case 3: act2 act0 + +Quale delle seguenti è la migliore stima della transition coverage per i test cases di cui sopra? \ No newline at end of file diff --git a/Ingegneria del Software/0922_13/wrong 1.txt b/Ingegneria del Software/0922_13/wrong 1.txt new file mode 100644 index 0000000..95bc750 --- /dev/null +++ b/Ingegneria del Software/0922_13/wrong 1.txt @@ -0,0 +1 @@ +100% \ No newline at end of file diff --git a/Ingegneria del Software/0922_13/wrong 2.txt b/Ingegneria del Software/0922_13/wrong 2.txt new file mode 100644 index 0000000..f91ad01 --- /dev/null +++ b/Ingegneria del Software/0922_13/wrong 2.txt @@ -0,0 +1 @@ +35% \ No newline at end of file diff --git a/Ingegneria del Software/0922_14/correct.txt b/Ingegneria del Software/0922_14/correct.txt new file mode 100644 index 0000000..7734d60 --- /dev/null +++ b/Ingegneria del Software/0922_14/correct.txt @@ -0,0 +1,71 @@ +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 0) and (pre(u) == 1) then x := 2; + +elseif (pre(x) == 0) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 1) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 1) and (pre(u) == 1) then x := 2; + +elseif (pre(x) == 1) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 3; + +elseif (pre(x) == 2) and (pre(u) == 1) then x := 0; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 3) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 1; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_14/quest.txt b/Ingegneria del Software/0922_14/quest.txt new file mode 100644 index 0000000..6afe072 --- /dev/null +++ b/Ingegneria del Software/0922_14/quest.txt @@ -0,0 +1,2 @@ +img=https://i.imgur.com/512MuK3.png +Quale dei seguenti modelli Modelica rappresenta lo state diagram in figura ? \ No newline at end of file diff --git a/Ingegneria del Software/0922_14/wrong 1.txt b/Ingegneria del Software/0922_14/wrong 1.txt new file mode 100644 index 0000000..fd1c3a4 --- /dev/null +++ b/Ingegneria del Software/0922_14/wrong 1.txt @@ -0,0 +1,71 @@ + +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 0) and (pre(u) == 1) then x := 1; + +elseif (pre(x) == 0) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 1) and (pre(u) == 1) then x := 2; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 2) and (pre(u) == 1) then x := 0; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 0; + +elseif (pre(x) == 3) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 3) and (pre(u) == 1) then x := 0; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 4; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 1; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; + diff --git a/Ingegneria del Software/0922_14/wrong 2.txt b/Ingegneria del Software/0922_14/wrong 2.txt new file mode 100644 index 0000000..763d3a6 --- /dev/null +++ b/Ingegneria del Software/0922_14/wrong 2.txt @@ -0,0 +1,69 @@ +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 1) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 1) and (pre(u) == 1) then x := 0; + +elseif (pre(x) == 1) and (pre(u) == 2) then x := 4; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 0; + +elseif (pre(x) == 2) and (pre(u) == 1) then x := 4; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 4; + +elseif (pre(x) == 3) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 3) and (pre(u) == 1) then x := 0; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 2; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_15/correct.txt b/Ingegneria del Software/0922_15/correct.txt new file mode 100644 index 0000000..2fd674f --- /dev/null +++ b/Ingegneria del Software/0922_15/correct.txt @@ -0,0 +1 @@ +60% \ No newline at end of file diff --git a/Ingegneria del Software/0922_15/quest.txt b/Ingegneria del Software/0922_15/quest.txt new file mode 100644 index 0000000..a64d8e6 --- /dev/null +++ b/Ingegneria del Software/0922_15/quest.txt @@ -0,0 +1,16 @@ +img=https://i.imgur.com/02dquYj.png +La transition coverage di un insieme di test cases (cioè sequenze di inputs) per uno state diagram è la percentuale di transizioni (archi nel grafo dello state diagram) percorsi almeno una volta. + +Si consideri lo state diagram in figura + + + +ed il seguente insieme di test cases: + +Test case 1: act0 + +Test case 2: act1 act0 act2 act2 act2 act0 act2 act1 act2 act0 act1 act0 + +Test case 3: act2 act0 + +Quale delle seguenti è la migliore stima della transition coverage per i test cases di cui sopra? \ No newline at end of file diff --git a/Ingegneria del Software/0922_15/wrong 1.txt b/Ingegneria del Software/0922_15/wrong 1.txt new file mode 100644 index 0000000..7b19605 --- /dev/null +++ b/Ingegneria del Software/0922_15/wrong 1.txt @@ -0,0 +1 @@ +75% \ No newline at end of file diff --git a/Ingegneria del Software/0922_15/wrong 2.txt b/Ingegneria del Software/0922_15/wrong 2.txt new file mode 100644 index 0000000..1e091a3 --- /dev/null +++ b/Ingegneria del Software/0922_15/wrong 2.txt @@ -0,0 +1 @@ +90% \ No newline at end of file diff --git a/Ingegneria del Software/0922_16/correct.txt b/Ingegneria del Software/0922_16/correct.txt new file mode 100644 index 0000000..8dd7202 --- /dev/null +++ b/Ingegneria del Software/0922_16/correct.txt @@ -0,0 +1 @@ +img=https://i.imgur.com/Zzrmwyx.png \ No newline at end of file diff --git a/Ingegneria del Software/0922_16/quest.txt b/Ingegneria del Software/0922_16/quest.txt new file mode 100644 index 0000000..df0415d --- /dev/null +++ b/Ingegneria del Software/0922_16/quest.txt @@ -0,0 +1,75 @@ +Si consideri il seguente modello Modelica. Quale dei seguenti state diagram lo rappresenta correttamente ? + + + +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 0) and (pre(u) == 1) then x := 4; + +elseif (pre(x) == 0) and (pre(u) == 2) then x := 3; + +elseif (pre(x) == 1) and (pre(u) == 1) then x := 2; + +elseif (pre(x) == 1) and (pre(u) == 2) then x := 0; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 0; + +elseif (pre(x) == 2) and (pre(u) == 1) then x := 1; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 3) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 1; + +elseif (pre(x) == 4) and (pre(u) == 2) then x := 1; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_16/wrong 1.txt b/Ingegneria del Software/0922_16/wrong 1.txt new file mode 100644 index 0000000..db7cce6 --- /dev/null +++ b/Ingegneria del Software/0922_16/wrong 1.txt @@ -0,0 +1 @@ +img=https://i.imgur.com/3ANMdkr.png \ No newline at end of file diff --git a/Ingegneria del Software/0922_16/wrong 2.txt b/Ingegneria del Software/0922_16/wrong 2.txt new file mode 100644 index 0000000..f0634e5 --- /dev/null +++ b/Ingegneria del Software/0922_16/wrong 2.txt @@ -0,0 +1 @@ +img=https://i.imgur.com/2RoLmLS.png \ No newline at end of file diff --git a/Ingegneria del Software/0922_17/correct.txt b/Ingegneria del Software/0922_17/correct.txt new file mode 100644 index 0000000..9a7cc7e --- /dev/null +++ b/Ingegneria del Software/0922_17/correct.txt @@ -0,0 +1,69 @@ +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 1) then x := 4; + +elseif (pre(x) == 1) and (pre(u) == 0) then x := 0; + +elseif (pre(x) == 1) and (pre(u) == 1) then x := 0; + +elseif (pre(x) == 1) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 2) and (pre(u) == 1) then x := 3; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 3; + +elseif (pre(x) == 3) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 3; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 2; + +elseif (pre(x) == 4) and (pre(u) == 2) then x := 2; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_17/quest.txt b/Ingegneria del Software/0922_17/quest.txt new file mode 100644 index 0000000..5ebf9be --- /dev/null +++ b/Ingegneria del Software/0922_17/quest.txt @@ -0,0 +1,2 @@ +img=https://i.imgur.com/WSvoelw.png +Quale dei seguenti modelli Modelica rappresenta lo state diagram in figura ? \ No newline at end of file diff --git a/Ingegneria del Software/0922_17/wrong 1.txt b/Ingegneria del Software/0922_17/wrong 1.txt new file mode 100644 index 0000000..b635e9d --- /dev/null +++ b/Ingegneria del Software/0922_17/wrong 1.txt @@ -0,0 +1,74 @@ + +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 0) and (pre(u) == 1) then x := 4; + +elseif (pre(x) == 0) and (pre(u) == 2) then x := 4; + +elseif (pre(x) == 1) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 1) and (pre(u) == 1) then x := 3; + +elseif (pre(x) == 1) and (pre(u) == 2) then x := 4; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 0; + +elseif (pre(x) == 2) and (pre(u) == 1) then x := 1; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 3) and (pre(u) == 1) then x := 4; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 3; + +elseif (pre(x) == 4) and (pre(u) == 2) then x := 3; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_17/wrong 2.txt b/Ingegneria del Software/0922_17/wrong 2.txt new file mode 100644 index 0000000..7006918 --- /dev/null +++ b/Ingegneria del Software/0922_17/wrong 2.txt @@ -0,0 +1,69 @@ +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 1) then x := 3; + +elseif (pre(x) == 0) and (pre(u) == 2) then x := 3; + +elseif (pre(x) == 1) and (pre(u) == 0) then x := 0; + +elseif (pre(x) == 1) and (pre(u) == 1) then x := 3; + +elseif (pre(x) == 1) and (pre(u) == 2) then x := 3; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 3; + +elseif (pre(x) == 2) and (pre(u) == 1) then x := 3; + +elseif (pre(x) == 3) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 3) and (pre(u) == 1) then x := 2; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 0; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 0; + +elseif (pre(x) == 4) and (pre(u) == 2) then x := 3; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_18/correct.txt b/Ingegneria del Software/0922_18/correct.txt new file mode 100644 index 0000000..9667516 --- /dev/null +++ b/Ingegneria del Software/0922_18/correct.txt @@ -0,0 +1 @@ +img=https://i.imgur.com/WRn8QOi.png \ No newline at end of file diff --git a/Ingegneria del Software/0922_18/quest.txt b/Ingegneria del Software/0922_18/quest.txt new file mode 100644 index 0000000..3d86edf --- /dev/null +++ b/Ingegneria del Software/0922_18/quest.txt @@ -0,0 +1,75 @@ +Si consideri il seguente modello Modelica. Quale dei seguenti state diagram lo rappresenta correttamente ? + +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 0) and (pre(u) == 1) then x := 2; + +elseif (pre(x) == 0) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 1) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 1) and (pre(u) == 1) then x := 0; + +elseif (pre(x) == 1) and (pre(u) == 2) then x := 3; + +elseif (pre(x) == 2) and (pre(u) == 1) then x := 1; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 0; + +elseif (pre(x) == 3) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 3) and (pre(u) == 1) then x := 1; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 0; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 1; + +elseif (pre(x) == 4) and (pre(u) == 2) then x := 1; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_18/wrong 1.txt b/Ingegneria del Software/0922_18/wrong 1.txt new file mode 100644 index 0000000..a9214bc --- /dev/null +++ b/Ingegneria del Software/0922_18/wrong 1.txt @@ -0,0 +1 @@ +img=https://i.imgur.com/oUj28ho.png \ No newline at end of file diff --git a/Ingegneria del Software/0922_18/wrong 2.txt b/Ingegneria del Software/0922_18/wrong 2.txt new file mode 100644 index 0000000..2a58fb7 --- /dev/null +++ b/Ingegneria del Software/0922_18/wrong 2.txt @@ -0,0 +1 @@ +img=https://i.imgur.com/eVnEYDY.png \ No newline at end of file diff --git a/Ingegneria del Software/0922_3/correct.txt b/Ingegneria del Software/0922_3/correct.txt new file mode 100644 index 0000000..faa122e --- /dev/null +++ b/Ingegneria del Software/0922_3/correct.txt @@ -0,0 +1 @@ +img=https://i.imgur.com/VgLa2I6.png \ No newline at end of file diff --git a/Ingegneria del Software/0922_3/quest.txt b/Ingegneria del Software/0922_3/quest.txt new file mode 100644 index 0000000..7159aee --- /dev/null +++ b/Ingegneria del Software/0922_3/quest.txt @@ -0,0 +1,77 @@ +Si consideri il seguente modello Modelica. Quale dei seguenti state diagram lo rappresenta correttamente ? + + + +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 0) and (pre(u) == 1) then x := 2; + +elseif (pre(x) == 1) and (pre(u) == 0) then x := 0; + +elseif (pre(x) == 1) and (pre(u) == 1) then x := 0; + +elseif (pre(x) == 1) and (pre(u) == 2) then x := 3; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 2) and (pre(u) == 1) then x := 3; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 3) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 3) and (pre(u) == 1) then x := 4; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 4; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 0; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 2; + +elseif (pre(x) == 4) and (pre(u) == 2) then x := 1; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_3/wrong 1.txt b/Ingegneria del Software/0922_3/wrong 1.txt new file mode 100644 index 0000000..6e77050 --- /dev/null +++ b/Ingegneria del Software/0922_3/wrong 1.txt @@ -0,0 +1 @@ +img=https://i.imgur.com/5MjNRI5.png \ No newline at end of file diff --git a/Ingegneria del Software/0922_3/wrong 2.txt b/Ingegneria del Software/0922_3/wrong 2.txt new file mode 100644 index 0000000..c7e9639 --- /dev/null +++ b/Ingegneria del Software/0922_3/wrong 2.txt @@ -0,0 +1 @@ +img=https://i.imgur.com/ugOv25D.png \ No newline at end of file diff --git a/Ingegneria del Software/0922_4/correct.txt b/Ingegneria del Software/0922_4/correct.txt new file mode 100644 index 0000000..7b19605 --- /dev/null +++ b/Ingegneria del Software/0922_4/correct.txt @@ -0,0 +1 @@ +75% \ No newline at end of file diff --git a/Ingegneria del Software/0922_4/quest.txt b/Ingegneria del Software/0922_4/quest.txt new file mode 100644 index 0000000..2eeb93f --- /dev/null +++ b/Ingegneria del Software/0922_4/quest.txt @@ -0,0 +1,16 @@ +img=https://i.imgur.com/PkKCYTb.png +La state coverage di un insieme di test cases (cioè sequenze di inputs) per uno state diagram è la percentuale di stati (inclusi START ed END) raggiunti almeno una volta. + +Si consideri lo state diagram in figura + + + +Si consideri il seguente insieme di test cases: + +Test case 1: act2 act0 act1 act1 act0 act2 act1 act2 act2 act1 act2 act0 act1 act2 act0 act2 act2 act0 act1 act1 act2 act2 act0 act0 act2 act2 act2 act0 act2 act0 act1 act1 act0 act2 act1 act2 act1 act0 act0 act0 act0 act2 act2 act1 act1 act1 act1 act0 + +Test case 2: act1 act2 act0 act2 act2 act1 act1 act0 act1 act2 act2 act0 + +Test case 3: act1 act1 act2 act0 act1 act0 + +Quale delle seguenti è la migliore stima della state coverage per i test cases di cui sopra \ No newline at end of file diff --git a/Ingegneria del Software/0922_4/wrong 1.txt b/Ingegneria del Software/0922_4/wrong 1.txt new file mode 100644 index 0000000..95bc750 --- /dev/null +++ b/Ingegneria del Software/0922_4/wrong 1.txt @@ -0,0 +1 @@ +100% \ No newline at end of file diff --git a/Ingegneria del Software/0922_4/wrong 2.txt b/Ingegneria del Software/0922_4/wrong 2.txt new file mode 100644 index 0000000..2fd674f --- /dev/null +++ b/Ingegneria del Software/0922_4/wrong 2.txt @@ -0,0 +1 @@ +60% \ No newline at end of file diff --git a/Ingegneria del Software/0922_5/correct.txt b/Ingegneria del Software/0922_5/correct.txt new file mode 100644 index 0000000..e0afa1b --- /dev/null +++ b/Ingegneria del Software/0922_5/correct.txt @@ -0,0 +1,67 @@ +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 0) and (pre(u) == 1) then x := 4; + +elseif (pre(x) == 0) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 1) and (pre(u) == 2) then x := 3; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 0; + +elseif (pre(x) == 2) and (pre(u) == 1) then x := 3; + +elseif (pre(x) == 3) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 2; + +elseif (pre(x) == 4) and (pre(u) == 2) then x := 1; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_5/quest.txt b/Ingegneria del Software/0922_5/quest.txt new file mode 100644 index 0000000..6cbb6d3 --- /dev/null +++ b/Ingegneria del Software/0922_5/quest.txt @@ -0,0 +1,2 @@ +img=https://i.imgur.com/XthureL.png +Quale dei seguenti modelli Modelica rappresenta lo state diagram in figura ? \ No newline at end of file diff --git a/Ingegneria del Software/0922_5/wrong 1.txt b/Ingegneria del Software/0922_5/wrong 1.txt new file mode 100644 index 0000000..53db382 --- /dev/null +++ b/Ingegneria del Software/0922_5/wrong 1.txt @@ -0,0 +1,69 @@ +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 0) and (pre(u) == 2) then x := 3; + +elseif (pre(x) == 1) and (pre(u) == 0) then x := 3; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 3; + +elseif (pre(x) == 2) and (pre(u) == 1) then x := 1; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 3; + +elseif (pre(x) == 3) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 3) and (pre(u) == 1) then x := 1; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 0; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 0; + +elseif (pre(x) == 4) and (pre(u) == 2) then x := 3; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_5/wrong 2.txt b/Ingegneria del Software/0922_5/wrong 2.txt new file mode 100644 index 0000000..11f8d0b --- /dev/null +++ b/Ingegneria del Software/0922_5/wrong 2.txt @@ -0,0 +1,71 @@ +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 1) then x := 2; + +elseif (pre(x) == 0) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 1) and (pre(u) == 0) then x := 3; + +elseif (pre(x) == 1) and (pre(u) == 1) then x := 3; + +elseif (pre(x) == 1) and (pre(u) == 2) then x := 4; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 2) and (pre(u) == 1) then x := 4; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 3; + +elseif (pre(x) == 3) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 1; + +elseif (pre(x) == 4) and (pre(u) == 1) then x := 0; + +elseif (pre(x) == 4) and (pre(u) == 2) then x := 0; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_6/correct.txt b/Ingegneria del Software/0922_6/correct.txt new file mode 100644 index 0000000..d494d0a --- /dev/null +++ b/Ingegneria del Software/0922_6/correct.txt @@ -0,0 +1 @@ +img=https://i.imgur.com/2GmgSsg.png \ No newline at end of file diff --git a/Ingegneria del Software/0922_6/quest.txt b/Ingegneria del Software/0922_6/quest.txt new file mode 100644 index 0000000..daf5598 --- /dev/null +++ b/Ingegneria del Software/0922_6/quest.txt @@ -0,0 +1,73 @@ +Si consideri il seguente modello Modelica. Quale dei seguenti state diagram lo rappresenta correttamente ? + + + +block FSA // Finite State Automaton + + + +/* connector declarations outside this block: + +connector InputInteger = input Integer; + +connector OutputInteger = output Integer; + +*/ + + + +InputInteger u; // external input + +OutputInteger x; // state + +parameter Real T = 1; + + + +algorithm + + + +when initial() then + +x := 0; + + + +elsewhen sample(0,T) then + + + +if (pre(x) == 0) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 0) and (pre(u) == 1) then x := 1; + +elseif (pre(x) == 0) and (pre(u) == 2) then x := 4; + +elseif (pre(x) == 1) and (pre(u) == 0) then x := 3; + +elseif (pre(x) == 2) and (pre(u) == 0) then x := 4; + +elseif (pre(x) == 2) and (pre(u) == 1) then x := 4; + +elseif (pre(x) == 2) and (pre(u) == 2) then x := 1; + +elseif (pre(x) == 3) and (pre(u) == 0) then x := 0; + +elseif (pre(x) == 3) and (pre(u) == 1) then x := 4; + +elseif (pre(x) == 3) and (pre(u) == 2) then x := 2; + +elseif (pre(x) == 4) and (pre(u) == 0) then x := 2; + +elseif (pre(x) == 4) and (pre(u) == 2) then x := 0; + +else x := pre(x); // default + +end if; + + + +end when; + +end FSA; \ No newline at end of file diff --git a/Ingegneria del Software/0922_6/wrong 1.txt b/Ingegneria del Software/0922_6/wrong 1.txt new file mode 100644 index 0000000..2a0dce8 --- /dev/null +++ b/Ingegneria del Software/0922_6/wrong 1.txt @@ -0,0 +1 @@ +img=https://i.imgur.com/vB4iDg8.png \ No newline at end of file diff --git a/Ingegneria del Software/0922_6/wrong 2.txt b/Ingegneria del Software/0922_6/wrong 2.txt new file mode 100644 index 0000000..e4e9137 --- /dev/null +++ b/Ingegneria del Software/0922_6/wrong 2.txt @@ -0,0 +1 @@ +img=https://i.imgur.com/5Mtuh64.png \ No newline at end of file diff --git a/Ingegneria del Software/0922_7/correct.txt b/Ingegneria del Software/0922_7/correct.txt new file mode 100644 index 0000000..fae4f5e --- /dev/null +++ b/Ingegneria del Software/0922_7/correct.txt @@ -0,0 +1 @@ +State coverage: 85% \ No newline at end of file diff --git a/Ingegneria del Software/0922_7/quest.txt b/Ingegneria del Software/0922_7/quest.txt new file mode 100644 index 0000000..d94d7c9 --- /dev/null +++ b/Ingegneria del Software/0922_7/quest.txt @@ -0,0 +1,15 @@ +img=https://i.imgur.com/YoZA1G0.png +La state coverage di un insieme di test cases (cioè sequenze di inputs) per uno state diagram è la percentuale di stati (inclusi START ed END) raggiunti almeno una volta. + +Si consideri lo state diagram in figura + + +Si consideri il seguente insieme di test cases: + +Test case 1: act1 act2 act2 act1 act2 act1 act1 act0 act1 act2 act0 act1 act2 act1 act2 act1 act0 act0 act2 act2 act0 act1 act1 act2 act2 act2 act0 act1 act2 act2 act1 + +Test case 2: act1 act2 act0 act0 act2 act2 act2 act2 act2 act1 act2 act0 act0 act2 act1 act2 act2 act2 act0 act0 act2 act1 act2 act2 act2 act0 act0 act1 + +Test case 3: act1 act1 + +Quale delle seguenti è la migliore stima della state coverage per i test cases di cui sopra \ No newline at end of file diff --git a/Ingegneria del Software/0922_7/wrong 1.txt b/Ingegneria del Software/0922_7/wrong 1.txt new file mode 100644 index 0000000..4e45af2 --- /dev/null +++ b/Ingegneria del Software/0922_7/wrong 1.txt @@ -0,0 +1 @@ +State coverage: 60% \ No newline at end of file diff --git a/Ingegneria del Software/0922_7/wrong 2.txt b/Ingegneria del Software/0922_7/wrong 2.txt new file mode 100644 index 0000000..d4625fd --- /dev/null +++ b/Ingegneria del Software/0922_7/wrong 2.txt @@ -0,0 +1 @@ +State coverage: 100% \ No newline at end of file diff --git a/Ingegneria del Software/0922_8/correct.txt b/Ingegneria del Software/0922_8/correct.txt new file mode 100644 index 0000000..4e45af2 --- /dev/null +++ b/Ingegneria del Software/0922_8/correct.txt @@ -0,0 +1 @@ +State coverage: 60% \ No newline at end of file diff --git a/Ingegneria del Software/0922_8/quest.txt b/Ingegneria del Software/0922_8/quest.txt new file mode 100644 index 0000000..983cffc --- /dev/null +++ b/Ingegneria del Software/0922_8/quest.txt @@ -0,0 +1,18 @@ +img=https://i.imgur.com/PqUZdeV.png +La state coverage di un insieme di test cases (cioè sequenze di inputs) per uno state diagram è la percentuale di stati (inclusi START ed END) raggiunti almeno una volta. + +Si consideri lo state diagram in figura + + +Si consideri il seguente insieme di test cases: + +Test case 1: act0 act2 + +Test case 2: act0 act0 act1 act1 act0 act1 act2 act0 act0 act1 act1 act2 act1 act2 act0 act0 act0 act2 + + +Test case 3: act2 act0 act1 act2 act2 + + + +Quale delle seguenti è la migliore stima della state coverage per i test cases di cui sopra \ No newline at end of file diff --git a/Ingegneria del Software/0922_8/wrong 1.txt b/Ingegneria del Software/0922_8/wrong 1.txt new file mode 100644 index 0000000..973ef63 --- /dev/null +++ b/Ingegneria del Software/0922_8/wrong 1.txt @@ -0,0 +1 @@ +State coverage: 75% \ No newline at end of file diff --git a/Ingegneria del Software/0922_8/wrong 2.txt b/Ingegneria del Software/0922_8/wrong 2.txt new file mode 100644 index 0000000..f6a4b07 --- /dev/null +++ b/Ingegneria del Software/0922_8/wrong 2.txt @@ -0,0 +1 @@ +State coverage: 90% \ No newline at end of file diff --git a/Ingegneria del Software/0922_9/correct.txt b/Ingegneria del Software/0922_9/correct.txt new file mode 100644 index 0000000..973ef63 --- /dev/null +++ b/Ingegneria del Software/0922_9/correct.txt @@ -0,0 +1 @@ +State coverage: 75% \ No newline at end of file diff --git a/Ingegneria del Software/0922_9/quest.txt b/Ingegneria del Software/0922_9/quest.txt new file mode 100644 index 0000000..13fde42 --- /dev/null +++ b/Ingegneria del Software/0922_9/quest.txt @@ -0,0 +1,17 @@ +img=https://i.imgur.com/dIi2Wn7.png +La state coverage di un insieme di test cases (cioè sequenze di inputs) per uno state diagram è la percentuale di stati (inclusi START ed END) raggiunti almeno una volta. + +Si consideri lo state diagram in figura + + +Si consideri il seguente insieme di test cases: + +Test case 1: act0 act0 act2 act1 act2 act0 act2 act0 act0 act0 act0 act0 act2 + +Test case 2: act1 act2 act1 act2 act0 act2 act1 act2 act2 + +Test case 3: act2 + + + +Quale delle seguenti è la migliore stima della state coverage per i test cases di cui sopra \ No newline at end of file diff --git a/Ingegneria del Software/0922_9/wrong 1.txt b/Ingegneria del Software/0922_9/wrong 1.txt new file mode 100644 index 0000000..f6a4b07 --- /dev/null +++ b/Ingegneria del Software/0922_9/wrong 1.txt @@ -0,0 +1 @@ +State coverage: 90% \ No newline at end of file diff --git a/Ingegneria del Software/0922_9/wrong 2.txt b/Ingegneria del Software/0922_9/wrong 2.txt new file mode 100644 index 0000000..4e45af2 --- /dev/null +++ b/Ingegneria del Software/0922_9/wrong 2.txt @@ -0,0 +1 @@ +State coverage: 60% \ No newline at end of file