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Refactor repo structure

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This commit is contained in:
Marco Realacci 2024-01-19 03:29:39 +01:00
parent 36ac339086
commit 8fc89fbc03
1732 changed files with 3812 additions and 67 deletions
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2
Data/Questions/ingsw/0210_9/quest.txt Normal file
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img=https://unspectacular-subdi.000webhostapp.com/0210_domanda_9.png
Quale dei seguenti modelli Modelica rappresenta lo state diagram in figura ?

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Data/Questions/ingsw/0210_9/wrong1.txt Normal file
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block FSA // Finite State Automaton
/* connector declarations outside this block:
connector InputInteger = input Integer;
connector OutputInteger = output Integer;
*/
InputInteger u; // external input
OutputInteger x; // state
parameter Real T = 1;
algorithm
when initial() then
x := 0;
elsewhen sample(0,T) then
if (pre(x) == 0) and (pre(u) == 1) then x := 2;
elseif (pre(x) == 0) and (pre(u) == 2) then x := 3;
elseif (pre(x) == 1) and (pre(u) == 0) then x := 4;
elseif (pre(x) == 1) and (pre(u) == 1) then x := 2;
elseif (pre(x) == 1) and (pre(u) == 2) then x := 2;
elseif (pre(x) == 2) and (pre(u) == 0) then x := 0;
elseif (pre(x) == 2) and (pre(u) == 1) then x := 4;
elseif (pre(x) == 2) and (pre(u) == 2) then x := 4;
elseif (pre(x) == 3) and (pre(u) == 0) then x := 1;
elseif (pre(x) == 3) and (pre(u) == 1) then x := 4;
elseif (pre(x) == 3) and (pre(u) == 2) then x := 2;
elseif (pre(x) == 4) and (pre(u) == 1) then x := 2;
elseif (pre(x) == 4) and (pre(u) == 2) then x := 2;
else x := pre(x); // default
end if;
end when;
end FSA;

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Data/Questions/ingsw/0210_9/wrong2.txt Normal file
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block FSA // Finite State Automaton
/* connector declarations outside this block:
connector InputInteger = input Integer;
connector OutputInteger = output Integer;
*/
InputInteger u; // external input
OutputInteger x; // state
parameter Real T = 1;
algorithm
when initial() then
x := 0;
elsewhen sample(0,T) then
if (pre(x) == 0) and (pre(u) == 0) then x := 2;
elseif (pre(x) == 0) and (pre(u) == 1) then x := 1;
elseif (pre(x) == 0) and (pre(u) == 2) then x := 3;
elseif (pre(x) == 1) and (pre(u) == 0) then x := 0;
elseif (pre(x) == 1) and (pre(u) == 1) then x := 4;
elseif (pre(x) == 2) and (pre(u) == 0) then x := 1;
elseif (pre(x) == 2) and (pre(u) == 1) then x := 0;
elseif (pre(x) == 3) and (pre(u) == 0) then x := 2;
elseif (pre(x) == 3) and (pre(u) == 1) then x := 2;
elseif (pre(x) == 3) and (pre(u) == 2) then x := 1;
elseif (pre(x) == 4) and (pre(u) == 0) then x := 3;
elseif (pre(x) == 4) and (pre(u) == 2) then x := 3;
else x := pre(x); // default
end if;
end when;
end FSA;

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Data/Questions/ingsw/0210_9/wrong3.txt Normal file
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block FSA // Finite State Automaton
/* connector declarations outside this block:
connector InputInteger = input Integer;
connector OutputInteger = output Integer;
*/
InputInteger u; // external input
OutputInteger x; // state
parameter Real T = 1;
algorithm
when initial() then
x := 0;
elsewhen sample(0,T) then
if (pre(x) == 0) and (pre(u) == 0) then x := 1;
elseif (pre(x) == 1) and (pre(u) == 0) then x := 0;
elseif (pre(x) == 1) and (pre(u) == 1) then x := 4;
elseif (pre(x) == 1) and (pre(u) == 2) then x := 2;
elseif (pre(x) == 2) and (pre(u) == 1) then x := 0;
elseif (pre(x) == 3) and (pre(u) == 0) then x := 1;
elseif (pre(x) == 3) and (pre(u) == 1) then x := 1;
elseif (pre(x) == 3) and (pre(u) == 2) then x := 2;
elseif (pre(x) == 4) and (pre(u) == 1) then x := 1;
else x := pre(x); // default
end if;
end when;
end FSA;